1. Field of the Invention
This invention relates to integrated circuit manufacture and more particularly to a system for transferring semiconductor wafers through a barrier between fabrication areas without transferring, through the barrier, the container which holds the wafers.
2. Description of the Relevant Art
An integrated circuit consists of electronic devices electrically coupled by conducting traces called interconnects. Interconnects are patterned from conducting layers formed on the surface of a semiconductor wafer. The ability to form stacked layers of interconnects has allowed more complex circuits to be implemented in and on relatively small surface areas of silicon substrates. The individual interconnect levels of multilevel interconnect structures are separated by layers of electrically insulating materials (i.e., interlevel dielectric layers).
As the number of interconnect levels is increased, the stacking of additional interconnect layers on top of one another tends to produce greater elevational disparity on the resulting surface topography. Problems of step coverage of a conductive layer upon the rugged topography oftentimes renders trace conductors inoperable or at least unreliable. In additional to step coverage problems, large disparity of the surface topography leads to depth of focus problems during photolithographic patterning of the conductive film to form trace conductors. Abrupt elevational changes in the topography of a semiconductor wafer typically occur at edges of patterned layers such as interconnects. The tendency of layers formed on the surface of a semiconductor wafer to be thinner over steps is referred to as the step coverage problem. A major factor in the processing of integrated circuits with submicron device dimensions is the limited depth of focus of the optical steppers used to pattern circuit features. In order to obtain maximum resolutions, imaging surfaces must be fairly planar with a suitable elevational disparity less than about .+-.0.5 microns. Accordingly, interlevel dielectric planarization techniques must be employed in order to make imaging surfaces substantially planar.
Chemical mechanical polish (CMP) is a popular method of planarizing the upper surface of an interlevel dielectric layer. CMP combines chemical etching and mechanical buffing to remove raised features on a surface of a semiconductor wafer. In a typical CMP process, a semiconductor wafer is mounted on a rotating holder and lowered onto a rotating surface flooded with a mild etchant solution, generally defined as a silica slurry. The etchant grows a thin layer on the exposed wafer surface that is almost simultaneously removed by the buffing action. The net effect is a very controlled polishing process capable of incredible flatness.
One problem with CMP techniques is that they produce large amounts of contaminants, including particulates, metallic ions, and chemical substances. The destructive effects of those contaminants is readily apparent in the overall performance of VLSI or ULSI devices. Any contaminants attributed to the slurry, chemical reactant, or buff/etch byproduct, which is thereafter introduced into other fabrication operations, severely compromises the success of those operations. For example, ingress of contaminants from the CMP operation to the thermal furnaces used for growing oxide, or to the chambers used for implanting ions, would negatively impact the resultant grown oxide or junction profile.
Without adequately preventing deposition of CMP-derived contaminants on semiconductor wafers undergoing other fabrication operations, CMP, as an interlevel dielectric planarization method, cannot be successfully used. One way to minimize deposition of CMP-derived contaminants on semiconductor wafers undergoing other (i.e., non-CMP) fabrication operations would be to perform the CMP process in an area hermetically sealed from other fabrication areas. Maintaining separate the CMP area from the other fabrication areas begins by installing a wall between those areas. Wafers must, however, be transported between the respective areas so that CMP can be incorporated within the process flow.
Transport of wafers between CMP and non-CMP areas entails passing the wafers through a door separating the areas. The door, depending upon sophistication, can be a load lock chamber adapted for passing a wafer-containing container. The wafer or wafers are transported in the container through the chamber from one area to another area. The load lock comprises an air circulation and filtration system which effectively flushes the ambient air surrounding the wafers. Unfortunately, however, the load lock by itself cannot in most instances remove contaminants from the surface of wafer-containing containers. The containers pick up contaminants while in the CMP fabrication area. When the containers passes through the load lock unit, those contaminants are not always flushed from the containers in the load lock. As a result, containers passed from one area to another may have contaminants clinging to them which may come loose and find their way onto the wafers.
It is therefore desirable to minimize the opportunity for a contaminated container from passing to and from a CMP area. An effective method of preventing passage of container-entrained contaminants into what should be a "clean room" environment from a relatively dirty CMP room is to pass only the wafers and not the containers in which they reside.
Robotic arms are now available which are able to accomplish many tedious and repetitive tasks previously performed by humans. Unlike a human, however, a robotic arm tirelessly performs such a task the same way every time, reducing variability in both the end result and the amount of time required to accomplish the task. The use of one or more robotic arms in a manufacturing process thus adds an element of predictability to the process.
It is therefore desirable to have an automated wafer transfer system which provides isolation between fabrication areas requiring different contamination control levels, yet provides for the transfer of semiconductor wafers between the fabrication areas. The wafer transfer system should pass only the semiconductor wafers from one fabrication area to another, and not the containers used to hold those wafers. The wafer transfer system should also be automated to reduce variability characteristic of manual operations